The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

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shengwenLiang
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Joined: Thu Jul 06, 2017 12:57 pm

The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

Post by shengwenLiang » Wed Sep 19, 2018 6:40 am

Hi, due to the datasheet document of Toggle Nand flash(H27Q1T8YEB9R-BCF) is confidential, and I want to know the block diagram of toggle NAND flash(H27Q1T8YEB9R-BCF) die? could you provide or descript?
when I read the micron chips dataset, the NAND flash array has two planes and each plan has own data register and cache register, so I want to know the Toggle NAND flash has the same architecture? Thanks.

KibinPark
Posts: 47
Joined: Thu Mar 30, 2017 9:25 am

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

Post by KibinPark » Wed Sep 19, 2018 7:29 am

H27Q1T8YEB9R-BCF has 2 LUNs per die, and each LUN has its own cache and data registers.
H27Q1T8YEB9R-BCF has 4CE, 4R/B, and it has dual channels NAND bus. (2CE, 2R/B per a channel)
The dual channels are merged into a single channel, and two single channels are also merged into a channel of the toggle NAND module for Cosmos.
Thus, one NAND channel of the toggle NAND module consists of two H27Q1T8YEB9R-BCF chips, which share a single NAND bus and have total 8CE and 8R/B.

shengwenLiang
Posts: 46
Joined: Thu Jul 06, 2017 12:57 pm

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

Post by shengwenLiang » Wed Sep 19, 2018 8:55 am

KibinPark wrote:
Wed Sep 19, 2018 7:29 am
H27Q1T8YEB9R-BCF has 2 LUNs per die, and each LUN has its own cache and data registers.
H27Q1T8YEB9R-BCF has 4CE, 4R/B, and it has dual channels NAND bus. (2CE, 2R/B per a channel)
The dual channels are merged into a single channel, and two single channels are also merged into a channel of the toggle NAND module for Cosmos.
Thus, one NAND channel of the toggle NAND module consists of two H27Q1T8YEB9R-BCF chips, which share a single NAND bus and have total 8CE and 8R/B.
Thanks for your reply, if I want to achieve read page cache sequential (31h) and read page multi-plane(00-32h), what should I do? Could i to modify the uOrogRom.coe file to support two commands?

and now I want to achieve transfer data in flash storage directly to computation engine without adding any data buffer. so I need add read page cache sequential command or read page multi-plane command to support the data in flash storage could directly transfer to computation engine without any stall status. As you say, the bandwidth of NAND flash controller is 4B/2cycle, that is mean that the 16bits data arrive at compute unit every cycle? please give me some advice.
Thanks

KibinPark
Posts: 47
Joined: Thu Mar 30, 2017 9:25 am

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

Post by KibinPark » Wed Sep 19, 2018 10:01 am

You should modify the controller RTL design to support the two commands.

The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %.

shengwenLiang
Posts: 46
Joined: Thu Jul 06, 2017 12:57 pm

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

Post by shengwenLiang » Thu Sep 20, 2018 12:16 am

KibinPark wrote:
Wed Sep 19, 2018 10:01 am
You should modify the controller RTL design to support the two commands.

The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %.
Thanks, as you say, now the bandwidth of the NFC is 4B/2cycle, and the data width is 4B and the bus utilization is 50%. And the toggle NAND flash could read data at rising edge and falling edge, which means that NAND flash could output 16bits (2*8bits) data every cycle? if I modify the RTL design, could I achieve read 16bits from NAND flash every cycle?

KibinPark
Posts: 47
Joined: Thu Mar 30, 2017 9:25 am

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

Post by KibinPark » Thu Sep 20, 2018 12:53 am

NAND could output 16 bits per cycle, and then they are merged into 32 bits per every 2 cycles. If you want a steady 16 bits output, add a bit width converter such as 32b-to-16b-FIFO.

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