The problem about NPhy_Toggle_Physical_Output_DDR100 module

Post Reply
shengwenLiang
Posts: 46
Joined: Thu Jul 06, 2017 12:57 pm

The problem about NPhy_Toggle_Physical_Output_DDR100 module

Post by shengwenLiang » Fri Nov 16, 2018 3:27 pm

Hi,
I read the Verilog code of NPhy_Toggle_Physical_Output_DDR100 and find the input iPO_DQ is 32bits and the comment says half res. Meanwhile, the oserdes2 module is used and configured to 4: 1 DDR. However, 4:1 DDR only transfer 4 bits to serial code. So the 32bits only 16bits can be written into the NAND flash. So I confuse why the iPO_DQ signal is 32bits and the oserdes2 only utilize the 16bits? Thanks.

input [31:0] iPO_DQ; // DQ, half res., 2 bit * 8 bit data width = 16 bit interface width
generate
for (c = 0; c < 8; c = c + 1)
begin : DQOSERDESBits
OSERDESE2
#
(
.DATA_RATE_OQ ("DDR" ),
//.DATA_RATE_TQ ("SDR" ),
.DATA_RATE_TQ ("BUF" ),
.DATA_WIDTH (4 ),
.INIT_OQ (1'b0 ),
.INIT_TQ (1'b1 ),
.SERDES_MODE ("MASTER" ),
.SRVAL_OQ (1'b0 ),
.SRVAL_TQ (1'b1 ),
.TRISTATE_WIDTH (1 )
)
Inst_DQOSERDES
(
.OFB ( ),
.OQ (oDQToNAND[c] ),
.SHIFTOUT1 ( ),
.SHIFTOUT2 ( ),
.TBYTEOUT ( ),
.TFB ( ),
.TQ (oDQOutEnableToPinpad[c]), // to pinpad

.CLK (iOutputDrivingClock),
.CLKDIV (iSystemClock ),
.D1 (iPO_DQ[ 0 + c] ),
.D2 (iPO_DQ[ 0 + c] ),
.D3 (iPO_DQ[ 8 + c] ),
.D4 (iPO_DQ[ 8 + c] ),
.D5 (iPO_DQ[16 + c] ),
.D6 (iPO_DQ[16 + c] ),
.D7 (iPO_DQ[24 + c] ),
.D8 (iPO_DQ[24 + c] ),

.OCE (1'b1 ),
.RST (iModuleReset ),
.SHIFTIN1 (0 ),
.SHIFTIN2 (0 ),
.T1 (rDQOut_IOBUF_T ), // from P.M.
.T2 (0 ),
.T3 (0 ),
.T4 (0 ),
.TBYTEIN (0 ),
.TCE (1'b1 )
);
end
endgenerate

KibinPark
Posts: 47
Joined: Thu Mar 30, 2017 9:25 am

Re: The problem about NPhy_Toggle_Physical_Output_DDR100 module

Post by KibinPark » Wed Nov 28, 2018 5:51 am

Legacy. Currently the serdes only utilizes 16 bits only.

Post Reply

Who is online

Users browsing this forum: No registered users and 1 guest