Search found 43 matches

by shengwenLiang
Thu Sep 20, 2018 5:50 am
Forum: HW Development Group
Topic: The power consumption of H27Q1T8YEB9R-BCF and openSSD
Replies: 1
Views: 8

The power consumption of H27Q1T8YEB9R-BCF and openSSD

Hi, Have you measured the power consumption of openSSD? when I run the 4Ch8Way project, the power meter shows the power consumption of openSSD is 17W, and when I read and write data to openSSD, the power consumption is about 20W. so I want to know the detail of the power consumption of NAND flash. c...
by shengwenLiang
Thu Sep 20, 2018 12:16 am
Forum: HW Development Group
Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
Replies: 5
Views: 31

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

You should modify the controller RTL design to support the two commands. The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %. Thanks, as you say, now the bandwidth of the NFC is 4B/2cycle, and the data width is 4B and the bus utilization ...
by shengwenLiang
Wed Sep 19, 2018 8:55 am
Forum: HW Development Group
Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
Replies: 5
Views: 31

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

H27Q1T8YEB9R-BCF has 2 LUNs per die, and each LUN has its own cache and data registers. H27Q1T8YEB9R-BCF has 4CE, 4R/B, and it has dual channels NAND bus. (2CE, 2R/B per a channel) The dual channels are merged into a single channel, and two single channels are also merged into a channel of the togg...
by shengwenLiang
Wed Sep 19, 2018 6:40 am
Forum: HW Development Group
Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
Replies: 5
Views: 31

The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

Hi, due to the datasheet document of Toggle Nand flash(H27Q1T8YEB9R-BCF) is confidential, and I want to know the block diagram of toggle NAND flash(H27Q1T8YEB9R-BCF) die? could you provide or descript? when I read the micron chips dataset, the NAND flash array has two planes and each plan has own da...
by shengwenLiang
Mon Aug 27, 2018 1:03 am
Forum: SW Development Group
Topic: How to modify firmware to support SPDK from intel
Replies: 0
Views: 43

How to modify firmware to support SPDK from intel

Hi, Recently, I want to use SPDK which is from Intel to achieve the communication between OpenSSD and user-level space. The SPDK could reduce the latency compared with traditional operation methods in Linux. However, when I use SPDK, I find I can't run the example "hello world" of SPDK. and I also a...
by shengwenLiang
Mon Aug 20, 2018 2:10 am
Forum: HW Development Group
Topic: The IDELAYCTRLS problem of V2NFC100DDR_1 and V2NFC100DDR_5
Replies: 1
Views: 43

The IDELAYCTRLS problem of V2NFC100DDR_1 and V2NFC100DDR_5

Hi, Recently, i upgrade the V2NFC100DDR ip from vivado 2014.2 to vivado 2018.2, and the synthesis has been run successfully, and when i run implementation, there are IDELAYCTRLS problem occurs that: [DRC PLIDC-7] IDELAYCTRLs not LOC or ungrouped: Design has more than one unlocked and ungrouped IDELA...
by shengwenLiang
Mon Jul 16, 2018 11:12 am
Forum: HW Development Group
Topic: Toggle Nand flash(H27Q1T8YEB9R-BCF) performance
Replies: 1
Views: 228

Toggle Nand flash(H27Q1T8YEB9R-BCF) performance

Hi, due to the datasheet document of Toggle Nand flash(H27Q1T8YEB9R-BCF) is confidential and now i want to know some performance details, such as the latency of read per page and program page and erase page?
could you provide?

Read page: (?) us
Program page: (?) us
Erase block (?)ms


Thanks
by shengwenLiang
Fri Jun 01, 2018 2:09 am
Forum: SW Development Group
Topic: The V2FStatusCheckAsync() function back status is 0x1FF01
Replies: 1
Views: 1506

The V2FStatusCheckAsync() function back status is 0x1FF01

Hi, Recently, i test fimeware in linux system, and modify the fmc_driver.c using mmap to map Tiger4NSC IP register to dram. then write register content to control then IP. example: void __attribute__((optimize("O0"))) V2FStatusCheckAsync(V2FMCRegisters* dev, int way, unsigned int* statusReport) { *(...
by shengwenLiang
Wed May 30, 2018 2:31 am
Forum: SW Development Group
Topic: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?
Replies: 4
Views: 1542

Re: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?

They are not necessary if you are going to run linux kernel. In addition, total DRAM size of Cosmos board is 1 GB. Hi, Thanks for your reply. Today, I test my idea and run linaro system in zynq FPGA. but when I migrate the openSSD firmware to Linux system. I face the problem that the function of fm...
by shengwenLiang
Mon May 28, 2018 8:58 am
Forum: SW Development Group
Topic: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?
Replies: 4
Views: 1542

Re: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?

Please refer to https://www.xilinx.com/products/design-tools/embedded-software/petalinux-sdk.html Hi, Thanks for your reply, when i create the Linux boot, i find that i don't know how to set this configuration in linux system. XScuGic_Config *IntcConfig; Xil_ICacheDisable(); Xil_DCacheDisable(); Xi...