OpenSSD Community Forum

Hi, I read the code of BCHEncoder, and find there is a CRCGenerator module. However, I find when rCmdType == ECCCtrlCmdType_SpareEncode . The CRCGenerator module is inactive because the wCRCEncable signal is set to 0. Meanwhile, when iCmdType == ECCCtrlCmdType_PageEncode, although the CRCGenerator m...

Hi, I read the Verilog code of NPhy_Toggle_Physical_Output_DDR100 and find the input iPO_DQ is 32bits and the comment says half res. Meanwhile, the oserdes2 module is used and configured to 4: 1 DDR. However, 4:1 DDR only transfer 4 bits to serial code. So the 32bits only 16bits can be written into ...

Hi， Now I want to added read page cache sequential command in Cosmos plus openSSD project. and as you said before, I need to modify the RTL code to support this command. So I want to know, what criteria should I follow to modify it? could you provide the toggle NAND flash simulation model? if can't ...

Hi, Have you measured the power consumption of openSSD? when I run the 4Ch8Way project, the power meter shows the power consumption of openSSD is 17W, and when I read and write data to openSSD, the power consumption is about 20W. so I want to know the detail of the power consumption of NAND flash. c...

You should modify the controller RTL design to support the two commands. The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %. Thanks, as you say, now the bandwidth of the NFC is 4B/2cycle, and the data width is 4B and the bus utilization ...

H27Q1T8YEB9R-BCF has 2 LUNs per die, and each LUN has its own cache and data registers. H27Q1T8YEB9R-BCF has 4CE, 4R/B, and it has dual channels NAND bus. (2CE, 2R/B per a channel) The dual channels are merged into a single channel, and two single channels are also merged into a channel of the togg...

Hi, due to the datasheet document of Toggle Nand flash(H27Q1T8YEB9R-BCF) is confidential, and I want to know the block diagram of toggle NAND flash(H27Q1T8YEB9R-BCF) die? could you provide or descript? when I read the micron chips dataset, the NAND flash array has two planes and each plan has own da...

Hi, Recently, I want to use SPDK which is from Intel to achieve the communication between OpenSSD and user-level space. The SPDK could reduce the latency compared with traditional operation methods in Linux. However, when I use SPDK, I find I can't run the example "hello world" of SPDK. and I also a...

Hi, Recently, i upgrade the V2NFC100DDR ip from vivado 2014.2 to vivado 2018.2, and the synthesis has been run successfully, and when i run implementation, there are IDELAYCTRLS problem occurs that: [DRC PLIDC-7] IDELAYCTRLs not LOC or ungrouped: Design has more than one unlocked and ungrouped IDELA...

Hi, due to the datasheet document of Toggle Nand flash(H27Q1T8YEB9R-BCF) is confidential and now i want to know some performance details, such as the latency of read per page and program page and erase page?
could you provide?

Read page: (?) us
Program page: (?) us
Erase block (?)ms


Thanks