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Legacy. Currently the serdes only utilizes 16 bits only.

Unfortunately, we cannot provide a NAND simulation model since we do not have any as well.

Single Die Operating Current
Page Read : 50 mA max.
Page Program : 50 mA max.
DQ Burst Read : 80 mA max.
DQ Burst Program: 80 mA max.
BUS Idle : 5 mA max.
Standby CMOS: 50 uA max.
VCC is 3.3v and VCCQ is 1.8v

NAND could output 16 bits per cycle, and then they are merged into 32 bits per every 2 cycles. If you want a steady 16 bits output, add a bit width converter such as 32b-to-16b-FIFO.

You should modify the controller RTL design to support the two commands.

The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %.

H27Q1T8YEB9R-BCF has 2 LUNs per die, and each LUN has its own cache and data registers. H27Q1T8YEB9R-BCF has 4CE, 4R/B, and it has dual channels NAND bus. (2CE, 2R/B per a channel) The dual channels are merged into a single channel, and two single channels are also merged into a channel of the toggl...

Here is my constr_nand_ch45.xdc file sample. Channel 4 and 5 should share a common IDELAYCTRL. set_property IODELAY_GROUP "BANK_4_IODELAY_GROUP" [get_cells V2NFC100DDR_4/inst/Inst_NPhy_Toggle_Top/Inst_NPhy_Toggle_Physical_Input/Inst_DQSIDELAYCTRL] set_property IODELAY_GROUP "BANK_4_IODELAY_GROUP" [g...

Here are some average values we measured.
Tread: 74-100 us
Tprog: 400-2300 us
Terase: 5 ms

You might need to check V2FIsControllerBusy before you issue a command.

They are not necessary if you are going to run linux kernel.
In addition, total DRAM size of Cosmos board is 1 GB.