Search found 47 matches
- Wed Nov 28, 2018 5:51 am
- Forum: HW Development Group
- Topic: The problem about NPhy_Toggle_Physical_Output_DDR100 module
- Replies: 1
- Views: 9736
Re: The problem about NPhy_Toggle_Physical_Output_DDR100 module
Legacy. Currently the serdes only utilizes 16 bits only.
- Mon Oct 01, 2018 1:34 am
- Forum: HW Development Group
- Topic: Could you provide Toggle Nand flash(H27Q1T8YEB9R-BCF) simulation model?
- Replies: 1
- Views: 4573
Re: Could you provide Toggle Nand flash(H27Q1T8YEB9R-BCF) simulation model?
Unfortunately, we cannot provide a NAND simulation model since we do not have any as well.
- Thu Sep 20, 2018 6:24 am
- Forum: HW Development Group
- Topic: The power consumption of H27Q1T8YEB9R-BCF and openSSD
- Replies: 1
- Views: 4335
Re: The power consumption of H27Q1T8YEB9R-BCF and openSSD
Single Die Operating Current
Page Read : 50 mA max.
Page Program : 50 mA max.
DQ Burst Read : 80 mA max.
DQ Burst Program: 80 mA max.
BUS Idle : 5 mA max.
Standby CMOS: 50 uA max.
VCC is 3.3v and VCCQ is 1.8v
Page Read : 50 mA max.
Page Program : 50 mA max.
DQ Burst Read : 80 mA max.
DQ Burst Program: 80 mA max.
BUS Idle : 5 mA max.
Standby CMOS: 50 uA max.
VCC is 3.3v and VCCQ is 1.8v
- Thu Sep 20, 2018 12:53 am
- Forum: HW Development Group
- Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
- Replies: 5
- Views: 17419
Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
NAND could output 16 bits per cycle, and then they are merged into 32 bits per every 2 cycles. If you want a steady 16 bits output, add a bit width converter such as 32b-to-16b-FIFO.
- Wed Sep 19, 2018 10:01 am
- Forum: HW Development Group
- Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
- Replies: 5
- Views: 17419
Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
You should modify the controller RTL design to support the two commands.
The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %.
The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %.
- Wed Sep 19, 2018 7:29 am
- Forum: HW Development Group
- Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
- Replies: 5
- Views: 17419
Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
H27Q1T8YEB9R-BCF has 2 LUNs per die, and each LUN has its own cache and data registers. H27Q1T8YEB9R-BCF has 4CE, 4R/B, and it has dual channels NAND bus. (2CE, 2R/B per a channel) The dual channels are merged into a single channel, and two single channels are also merged into a channel of the toggl...
- Wed Aug 22, 2018 10:22 am
- Forum: HW Development Group
- Topic: The IDELAYCTRLS problem of V2NFC100DDR_1 and V2NFC100DDR_5
- Replies: 1
- Views: 4190
Re: The IDELAYCTRLS problem of V2NFC100DDR_1 and V2NFC100DDR_5
Here is my constr_nand_ch45.xdc file sample. Channel 4 and 5 should share a common IDELAYCTRL. set_property IODELAY_GROUP "BANK_4_IODELAY_GROUP" [get_cells V2NFC100DDR_4/inst/Inst_NPhy_Toggle_Top/Inst_NPhy_Toggle_Physical_Input/Inst_DQSIDELAYCTRL] set_property IODELAY_GROUP "BANK_4_IODELAY_GROUP" [g...
- Mon Jul 16, 2018 11:54 am
- Forum: HW Development Group
- Topic: Toggle Nand flash(H27Q1T8YEB9R-BCF) performance
- Replies: 1
- Views: 4610
Re: Toggle Nand flash(H27Q1T8YEB9R-BCF) performance
Here are some average values we measured.
Tread: 74-100 us
Tprog: 400-2300 us
Terase: 5 ms
Tread: 74-100 us
Tprog: 400-2300 us
Terase: 5 ms
- Fri Jun 01, 2018 10:34 am
- Forum: SW Development Group
- Topic: The V2FStatusCheckAsync() function back status is 0x1FF01
- Replies: 1
- Views: 5541
Re: The V2FStatusCheckAsync() function back status is 0x1FF01
You might need to check V2FIsControllerBusy before you issue a command.
- Mon May 28, 2018 9:09 am
- Forum: SW Development Group
- Topic: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?
- Replies: 4
- Views: 17343
Re: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?
They are not necessary if you are going to run linux kernel.
In addition, total DRAM size of Cosmos board is 1 GB.
In addition, total DRAM size of Cosmos board is 1 GB.