Search found 45 matches

by KibinPark
Thu Sep 20, 2018 6:24 am
Forum: HW Development Group
Topic: The power consumption of H27Q1T8YEB9R-BCF and openSSD
Replies: 1
Views: 8

Re: The power consumption of H27Q1T8YEB9R-BCF and openSSD

Single Die Operating Current
Page Read : 50 mA max.
Page Program : 50 mA max.
DQ Burst Read : 80 mA max.
DQ Burst Program: 80 mA max.
BUS Idle : 5 mA max.
Standby CMOS: 50 uA max.
VCC is 3.3v and VCCQ is 1.8v
by KibinPark
Thu Sep 20, 2018 12:53 am
Forum: HW Development Group
Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
Replies: 5
Views: 31

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

NAND could output 16 bits per cycle, and then they are merged into 32 bits per every 2 cycles. If you want a steady 16 bits output, add a bit width converter such as 32b-to-16b-FIFO.
by KibinPark
Wed Sep 19, 2018 10:01 am
Forum: HW Development Group
Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
Replies: 5
Views: 31

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

You should modify the controller RTL design to support the two commands.

The bandwidth of the NFC is 4B/2cycle, which means that the bus data width is 4B and the bus utilization is 50 %.
by KibinPark
Wed Sep 19, 2018 7:29 am
Forum: HW Development Group
Topic: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)
Replies: 5
Views: 31

Re: The data register and cache register of toggle nand flash(H27Q1T8YEB9R-BCF)

H27Q1T8YEB9R-BCF has 2 LUNs per die, and each LUN has its own cache and data registers. H27Q1T8YEB9R-BCF has 4CE, 4R/B, and it has dual channels NAND bus. (2CE, 2R/B per a channel) The dual channels are merged into a single channel, and two single channels are also merged into a channel of the toggl...
by KibinPark
Wed Aug 22, 2018 10:22 am
Forum: HW Development Group
Topic: The IDELAYCTRLS problem of V2NFC100DDR_1 and V2NFC100DDR_5
Replies: 1
Views: 45

Re: The IDELAYCTRLS problem of V2NFC100DDR_1 and V2NFC100DDR_5

Here is my constr_nand_ch45.xdc file sample. Channel 4 and 5 should share a common IDELAYCTRL. set_property IODELAY_GROUP "BANK_4_IODELAY_GROUP" [get_cells V2NFC100DDR_4/inst/Inst_NPhy_Toggle_Top/Inst_NPhy_Toggle_Physical_Input/Inst_DQSIDELAYCTRL] set_property IODELAY_GROUP "BANK_4_IODELAY_GROUP" [g...
by KibinPark
Mon Jul 16, 2018 11:54 am
Forum: HW Development Group
Topic: Toggle Nand flash(H27Q1T8YEB9R-BCF) performance
Replies: 1
Views: 228

Re: Toggle Nand flash(H27Q1T8YEB9R-BCF) performance

Here are some average values we measured.
Tread: 74-100 us
Tprog: 400-2300 us
Terase: 5 ms
by KibinPark
Fri Jun 01, 2018 10:34 am
Forum: SW Development Group
Topic: The V2FStatusCheckAsync() function back status is 0x1FF01
Replies: 1
Views: 1512

Re: The V2FStatusCheckAsync() function back status is 0x1FF01

You might need to check V2FIsControllerBusy before you issue a command.
by KibinPark
Mon May 28, 2018 9:09 am
Forum: SW Development Group
Topic: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?
Replies: 4
Views: 1543

Re: Could to run linux system on the zynq fpga of OpenSSD to control the write and read?

They are not necessary if you are going to run linux kernel.
In addition, total DRAM size of Cosmos board is 1 GB.
by KibinPark
Wed May 23, 2018 11:21 am
Forum: SW Development Group
Topic: How to set MLC_MODE in GreedyFTL-2.7.1.d project
Replies: 1
Views: 619

Re: How to set MLC_MODE in GreedyFTL-2.7.1.d project

The storage capacity is limited because the system memory is not enough to contain the entire mapping table. You might need some additional scheme such as DFTL and MapCache.